===== Activate the LM4F/TM4C with a 16 MHz crystal to run at 80 MHz =====

  void PLL_Init(void){
    // 0) Use RCC2
    SYSCTL_RCC2_R |=  0x80000000;  // USERCC2
    // 1) bypass PLL while initializing
    SYSCTL_RCC2_R |=  0x00000800;  // BYPASS2, PLL bypass
    // 2) select the crystal value and oscillator source
    SYSCTL_RCC_R = (SYSCTL_RCC_R &~0x000007C0)   // clear XTAL field, bits 10-6
                 + 0x00000540;   // 10101, configure for 16 MHz crystal
    SYSCTL_RCC2_R &= ~0x00000070;  // configure for main oscillator source
    // 3) activate PLL by clearing PWRDN
    SYSCTL_RCC2_R &= ~0x00002000;
    // 4) set the desired system divider
    SYSCTL_RCC2_R |= 0x40000000;   // use 400 MHz PLL
    SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~ 0x1FC00000)  // clear system clock divider
                  + (4<<22);      // configure for 80 MHz clock
    // 5) wait for the PLL to lock by polling PLLLRIS
    while((SYSCTL_RIS_R&0x00000040)==0){};  // wait for PLLRIS bit
    // 6) enable use of PLL by clearing BYPASS
    SYSCTL_RCC2_R &= ~0x00000800;
  }


^ XTAL ^ Crystal Freq (MHz)^
| 0x00 | Reserved |
| 0x01 | Reserved |
| 0x02 | Reserved |
| 0x03 | Reserved |
| 0x04 | 3.579545 MHz |
| 0x05 | 3.6864 MHz |
| 0x06 | 4 MHz |
| 0x07 | 4.096 MHz |
| 0x08 | 4.9152 MHz |
| 0x09 | 5 MHz |
| 0x0A | 5.12 MHz |
| 0x0B | 6 MHz (reset value) |
| 0x0C | 6.144 MHz |
| 0x0D | 7.3728 MHz |
| 0x0E | 8 MHz |
| 0x0F | 8.192 MHz |
| 0x10 | 10.0 MHz |
| 0x11 | 12.0 MHz |
| 0x12 | 12.288 MHz |
| 0x13 | 13.56 MHz |
| 0x14 | 14.31818 MHz |
| 0x15 | 16.0 MHz |
| 0x16 | 16.384 MHz |
| 0x17 | 18.0 MHz |
| 0x18 | 20.0 MHz |
| 0x19 | 24.0 MHz |
| 0x1A | 25.0 MHz |
| 0x1B | Reserved |
| 0x1C | Reserved |
| 0x1D | Reserved |
| 0x1E | Reserved |
| 0x1F | Reserved |